Professional

My career in the electronics industry began in 1978 fresh out of high school. My passion for music, natural curiosity, and tinkering with building my own equipment were the stepping stones to my career. My work covers industrial controls, medical equipment, broadband internet cable delivery systems, and the majority of my career (24 years) working on video sensors & video cameras

During my early days I started out working on medical x-ray cameras utilizing vidicon & plumicon tubes. Another 8 years working on industrial cameras utilizing CID Imagers. Since 1998 my work has been entirely dedicated to designing CMOS linear & 2D array sensors for the motion picture industry, high res UDTV(4XHDTV), scientific, machine vision, and high volume consumer markets. Company Founder Panavision Imaging, LLC. (Prior to 2003: Photon Vision Systems, Inc) Current Title: Imager Design & Layout Engineer, Documentation Manager: Responsible for linear array product line. Image sensor silicon design & layout, schematic entry, and simulation for 1.5 thru 0.18 micron CMOS processes. FPGA design, PCB design/layout. Documentation Manager: oversee & implement processes, procedures, documentation control, and training.

Primary Management / Technical Duties:

Program manager -sensor projects.
CAD/CAE Department manger : Physical Layout- Silicon, PCB, Mechanical, other artwork/graphics
CMOS Image sensor silicon design & layout, schematic entry, for 1.5um, 0.5, 0.35, and 0.18um processes.
Full chip integration, Custom Analog, PLL, DACS, Distributed A/D, Pixels, Pitched Amplifiers, Discreet Amplifiers, Pitched Row Select Blocks, Highly Compacted Pitched Digital blocks, Pad frames & I/O. Area Array Sensors ≥ 37mp, 14bit LVDS outputs, w/full onboard programmable timing. Linear Arrays ≥ 32k, 12bit or Analog outputs, w/full onboard programmable timing.
Calibre DRC, LVS verification, GDS Mask Tape Outs, Foundry submittal
Develop / Review 3^rd party PCB projects, and custom sensor packaging

Other Management / Technical Duties:

Assist in accessing customer requirements, feasibility, and specifications. Customer application support
Marketing support- demo prep, graphics/artwork and trade show booth duties
Documentation Manager (1998-2009): oversee & implement processes, procedures, documentation control, and training. (2009-Present) Sign off for engineering, and consult on ISO9001/documentation issues
PCB design/layout.
Mechanical- bond diagrams, package drawings, and data sheet supporting views.
Electro Optical & debug testing, prototype/jig design & fixturing
FPGA design

IC Layout

Tanner L-edit Pro / LVS / S-edit , Calibre IC Layout / DRC / LVS , Virtuoso XL Layout

PCB Layout

IPC Designers Council # 1021032:

C.I.D. Certified Interconnect Designer, Certified 1999

C.I.D.+ Advanced Certified Interconnect Designer, Certified 2006

PowerPCB 4.0, Power Logic 4.0, CAM350, Orcad, ViewLogic

Patents

"A Video Bus For High Speed Multi-Resolution Imagers " Zarnowski Jeffrey; Joyner Michael; Pace Matthew; Vogelsong Thomas, July-8-2003 Patent: US 6,590,198

"A Video Bus For High Speed Multi-Resolution Imagers And Method Thereof" Zarnowski Jeffrey; Joyner Michael; Pace Matthew; Vogelsong Thomas, October-14-2003 Patents: (US) 6,633,029 (China) PCT/US01/02309 (European) PCT/US02/01864, PCT/US01/02309 (Japan) 2001-553588 (Taiwan) 90101651

“Scanning Image Employing Multiple Chips With Staggered Pixels” Zarnowski; Jeffrey J.; Karia; Ketan V.; Joyner; Michael; Poonnen; Thomas, May-16-2006 Patent: US 7,045,758

"Solid State Imager With Reduced Number Of Transistors Per Pixel" Zarnowski; Jeffrey J.; Ambalavanar; Samuel D. ; Joyner; Michael; Karia; Ketan V. June-6-2006 Patent: US 7,057,150

“Scanning imager employing multiple chips with staggered pixels” Zarnowski; Jeffrey J.; Karia; Ketan V.; Joyner; Michael; Poonnen; Thomas, Oct-17-2006 Patent: US 7,122,778 Oct-31-2006 Patent: 7,129,461 June-30-2009 Patent: 7,554,067

“Scanning imager employing multiple chips with staggered pixels” Zarnowski; Jeffrey J.; Karia; Ketan V.; Joyner; Michael; Poonnen; Thomas; Liu; Li, Febr-22-2007 Patent Application Publication: US 2007/0040100 A1

“Image sensor ADC and CDS per Column with Oversampling” Zarnowski; Jeffrey J.; Liu; Li; Joyner; Michael; Karia; Ketan V., Feb-21-2008 Patent Application Publication: US 2008/0043128 A1

“Image Sensor ADC and CDS per Column” Zarnowski; Jeffrey J.; Karia; Ketan V.; Joyner; Michael; Poonnen; Thomas, Sept-19-2009 Patent Application Publication: US 2009/0231479 A1

“Sub-Pixel Array Optical Sensor” Liu; Li; Zarnowski; Jeffrey J.; Karia; Ketan V.; Joyner; Michael; Poonnen; Thomas, Nov-26-2009 Patent Application Publication: US 2009/0290043 A1

“Color Pixel Pattern Scheme for High Dynamic Range Optical Sensor” Liu; Li; Zarnowski; Jeffrey J.; Karia; Ketan V.; Joyner; Michael; Poonnen; Thomas, Nov-26-2009 Patent Application Publication: US 2009/0290052 A1

“Increasing The Resolution Of Color Sub-Pixel Arrays” Zarnowski; Jeffrey J.; Karia; Ketan V.; Joyner; Michael; Poonnen; Thomas; Liu; Li, Jun-17-2010 Patent Application Publication: US 2007/0149393 A1

Publications

Poonnen, T. Li Liu Karia, K.V. Joyner, M.E. Zarnowski, J.J. “A CMOS video sensor for High Dynamic Range (HDR) imaging“ Panavision Imaging, LLC, Homer, NY;, 2008 42^nd IEEE Asilomar Conference on Signals, Systems and Computers’ Publication Date: 26-29 Oct. IEEE Link

R. M. Iodice, M. Joyner, C. S. Hong, D. Parker, Photon Vision Systems, Inc. “Broadcast quality 3840 x 2160 color imager operating at 30 frames/s,”, Proc. SPIE Vol. 5017-01. Jan 2003 Santa Clara, CA. SPIE Link

R. M. Iodice, J. Zarnowski, M. Pace and M. Joyner, T. L. Vogelsong, T. L. Zarnowski, Photon Vision Systems, Inc., “Ultrahigh-speed CMOS scanning linear imager family”, Proc. SPIE Vol. 4306, p. 100-110 Jan 2001, San Jose, CA. SPIE Link

J. Zarnowski, M. Pace and M. Joyner, “CMOS sensors overcome bad image and early hype”, Laser Focus World, July 1999, Penwell.

J. Zarnowski, M. Pace and M. Joyner, “1.5 FET per Pixel Standard CMOS Active Column Sensor”, SPIE Vol. 3649-27, Jan 1999. SPIE Link

J. Zarnowski, B. Williams, M. Pace, M. Joyner, J. Carbone, C. Borman, F.S. Arnold, and M. Wadsworth, “Selectable One to Four Port Very, High speed 512 X 512 CID”, SPIE, CCD and Solid State Optical Sensors Vol. 1447-18, February 1991, San Jose, CA. SPIE Link

Resume

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